Kirjoittaja PetriK » 16 Marras 2007, 22:36
Tässä mitä bozo lähetti. Tämä vaikuttaisi toimivan parallaxilla:
{
AUD PROBE
Mark Wrigley
NOVEMBER 2007
PA3 17 Nov 07
1. removed unused code
2. added full comments
PA2 16 Nov 07
1. corrected an error in the routine that sends address to AUDATA lines
it was rotating right temp1, but was sending Addr to AUDATA
correction sends temp1 to AUDATA
2. modified the wait loop that waits for a ready condition from the ECU
previous: loop 10 times
now: break out of loop after 10 loops or a ready/OK signal (%0001)
3. modified code after the wait loop to prevent trying to read AUDATA if
the wait loop executed 10 times ... program ends if this happens
4. eliminated SendLong ... send data to hyperterminal all contained in the main routine
5a.7052 datasheet specifies 5v for AUDRST and AUDMD. Since AUDMD is pulled high internally
if not connected, no need to set it. AUDRST interface should be o/p low to pull low,
and change to an input to let an external pullup resistor pull the line high to 5v.
Reset routine modified.
5b.A similar arrangement can be used for AUDMD if necessary. The datasheet says AUDMD will
be pulled high if unconnected, so probably no need to implement this?
6. Clock pulses are needed at RST/MD reset and mode setting, added at RAM_Mode
7. check AUD timing, clock should be high,low,high or low,high,low?
answer: high-low-high
8. modified clock pulse timing when reading back from the 7052
9. outputs from 7052 are 5v ... need to use say 1k resistors to limit current into propeller
on the AUDATA lines
}
CON
_clkmode = xtal1 + pll16x
_xinfreq = 5_000_000
'┌─────────────────────┐
'│ PIN ALLOCATIONS │
'└─────────────────────┘
pin_AUDRST = 7
pin_AUDMD = 6
pin_AUDATA0 = 5
pin_AUDATA1 = 4
pin_AUDATA2 = 3
pin_AUDATA3 = 2
pin_AUDSYNC = 1
pin_AUDCK = 0
clkrate = 10000
input = 0
output = 1
OBJ
Debug : "FullDuplexSerialPlus"
VAR
'┌─────────────────────┐
'│ COG STACKS ETC │
'└─────────────────────┘
long Stack1[19], Stack2[19], Stack3[9]
byte DebugCog
'┌─────────────────────┐
'│ VARIABLES │
'└─────────────────────┘
long Addr
long ReadBits
byte temp
byte i
PUB Main
DebugCog := Debug.start(31, 30, 0, 57600) 'start the serial comms
i := 0 'initialise i
dira[pin_AUDRST]~ 'RST pin is input (pulled high externally)
outa[pin_AUDRST] := 0 'RST will be pulled low when dira makes it an output
AUDATA(output) 'all AUDATA pins are output
dira[pin_AUDSYNC]~~ 'SYNC pin is output
dira[pin_AUDCK]~~ 'CK pin is output
outa[pin_AUDCK] := 1 'added PA2, set clock high
outa[pin_AUDSYNC] := 1 'pull SYNC line high
waitcnt(clkfreq*10+cnt) '10-sec delay to allow time to connect hyperterminal
'the USB is shared between IDE and hyperterminal
debug.str(String(13,10))
debug.str(String("Start...",13,10))
'set the starting address
Addr := 0
RAM_Mode 'AUD mode selection
repeat
ReadByte 'get byte from current Addr
Addr := Addr+1 'bump Addr
until Addr==0 or i==10 'do this until Addr reaches zero,
'or until hitting an error condition, whichever comes first
if i==10 'i.e. error
debug.str(String("error",13,10))
else 'i.e. no error
debug.str(String("done",13,10))
'END OF CODE EXECUTION
PUB RAM_Mode
dira[pin_AUDRST]~~ 'RST now an output
outa[pin_AUDRST] := 0 'RST pulled low
repeat 10
ClockPulse
dira[pin_AUDRST]~ 'restore RST to input, pulled high by external resistor
repeat 10 'these clocks probably not needed,
ClockPulse 'but I guess they can't hurt
PUB ReadByte | temp1, temp2
repeat 5 'probably only one clock pulse is needed here?
ClockPulse
outa[pin_AUDSYNC] := 0 'SYNC pulled low
' send 0000
outa[pin_AUDATA3] := 0
outa[pin_AUDATA2] := 0
outa[pin_AUDATA1] := 0
outa[pin_AUDATA0] := 0
ClockPulse
' send command to read byte (1000) ... read longword is 1010
outa[pin_AUDATA3] := 1
outa[pin_AUDATA2] := 0
outa[pin_AUDATA1] := 0
outa[pin_AUDATA0] := 0
ClockPulse
temp1 := Addr 'temp1 = next address to read
repeat 8 'send nibbles 8 times (total 32 bits)
outa[pin_AUDATA3..pin_AUDATA0] := temp1 'send 4 LSBs of address to AUDATA pins
ClockPulse 'clock them out
temp1 := temp1 >> 4 'rotate address right by 4 bits
AUDATA(input) 'prepare AUDATA lines as inputs
debug.str(String(13,10)) 'write address to hyperterminal
debug.hex(Addr,8)
debug.str(String(","))
'read in data until AUD is ready (0001)
i := 0
repeat
i++
temp := 0
ClockPulse
temp := ina[pin_AUDATA3..pin_AUDATA0] 'read in the data
until temp == %00000001 or i == 10
outa[pin_AUDSYNC] := 1 'SYNC pulled high
if i <> 10 'i.e. 7052 is ready and no errors
temp1 := 0
temp2 := 0
repeat 2 'read 4-bit nibbles from AUDATA lines
temp1 := temp1 << 4 'shift temp1 4 bits to the left
ClockPulse 'clock in the next set of AUDATA bits
temp2 := 0 'clear temp2
temp2 := ina[pin_AUDATA3..pin_AUDATA0] 'temp2 = received data from the ECU
temp1 := temp1 | temp2 'temp2 added on to the shifted temp1 value
ReadBits := temp1 'store result in ReadBits
debug.hex(ReadBits,8)
debug.str(String(","))
AUDATA(output) 'restore AUDATA pins to outputs
PUB ClockPulse
'send clock low then high
waitcnt(clkfreq/(clkrate/2) + cnt)
outa[pin_AUDCK] := 0
waitcnt(clkfreq/clkrate + cnt)
outa[pin_AUDCK] := 1
waitcnt(clkfreq/(clkrate/2) + cnt)
PUB AUDATA(direction)
if direction == input
dira[pin_AUDATA0]~
dira[pin_AUDATA1]~
dira[pin_AUDATA2]~
dira[pin_AUDATA3]~
if direction == output
dira[pin_AUDATA0]~~
dira[pin_AUDATA1]~~
dira[pin_AUDATA2]~~
dira[pin_AUDATA3]~~
[color=#000000]Tässä mitä bozo lähetti. Tämä vaikuttaisi toimivan parallaxilla:
{
AUD PROBE
Mark Wrigley
NOVEMBER 2007
PA3 17 Nov 07
1. removed unused code
2. added full comments
PA2 16 Nov 07
1. corrected an error in the routine that sends address to AUDATA lines
it was rotating right temp1, but was sending Addr to AUDATA
correction sends temp1 to AUDATA
2. modified the wait loop that waits for a ready condition from the ECU
previous: loop 10 times
now: break out of loop after 10 loops or a ready/OK signal (%0001)
3. modified code after the wait loop to prevent trying to read AUDATA if
the wait loop executed 10 times ... program ends if this happens
4. eliminated SendLong ... send data to hyperterminal all contained in the main routine
5a.7052 datasheet specifies 5v for AUDRST and AUDMD. Since AUDMD is pulled high internally
if not connected, no need to set it. AUDRST interface should be o/p low to pull low,
and change to an input to let an external pullup resistor pull the line high to 5v.
Reset routine modified.
5b.A similar arrangement can be used for AUDMD if necessary. The datasheet says AUDMD will
be pulled high if unconnected, so probably no need to implement this?
6. Clock pulses are needed at RST/MD reset and mode setting, added at RAM_Mode
7. check AUD timing, clock should be high,low,high or low,high,low?
answer: high-low-high
8. modified clock pulse timing when reading back from the 7052
9. outputs from 7052 are 5v ... need to use say 1k resistors to limit current into propeller
on the AUDATA lines
}
CON
_clkmode = xtal1 + pll16x
_xinfreq = 5_000_000
'┌─────────────────────┐
'│ PIN ALLOCATIONS │
'└─────────────────────┘
pin_AUDRST = 7
pin_AUDMD = 6
pin_AUDATA0 = 5
pin_AUDATA1 = 4
pin_AUDATA2 = 3
pin_AUDATA3 = 2
pin_AUDSYNC = 1
pin_AUDCK = 0
clkrate = 10000
input = 0
output = 1
OBJ
Debug : "FullDuplexSerialPlus"
VAR
'┌─────────────────────┐
'│ COG STACKS ETC │
'└─────────────────────┘
long Stack1[19], Stack2[19], Stack3[9]
byte DebugCog
'┌─────────────────────┐
'│ VARIABLES │
'└─────────────────────┘
long Addr
long ReadBits
byte temp
byte i
PUB Main
DebugCog := Debug.start(31, 30, 0, 57600) 'start the serial comms
i := 0 'initialise i
dira[pin_AUDRST]~ 'RST pin is input (pulled high externally)
outa[pin_AUDRST] := 0 'RST will be pulled low when dira makes it an output
AUDATA(output) 'all AUDATA pins are output
dira[pin_AUDSYNC]~~ 'SYNC pin is output
dira[pin_AUDCK]~~ 'CK pin is output
outa[pin_AUDCK] := 1 'added PA2, set clock high
outa[pin_AUDSYNC] := 1 'pull SYNC line high
waitcnt(clkfreq*10+cnt) '10-sec delay to allow time to connect hyperterminal
'the USB is shared between IDE and hyperterminal
debug.str(String(13,10))
debug.str(String("Start...",13,10))
'set the starting address
Addr := 0
RAM_Mode 'AUD mode selection
repeat
ReadByte 'get byte from current Addr
Addr := Addr+1 'bump Addr
until Addr==0 or i==10 'do this until Addr reaches zero,
'or until hitting an error condition, whichever comes first
if i==10 'i.e. error
debug.str(String("error",13,10))
else 'i.e. no error
debug.str(String("done",13,10))
'END OF CODE EXECUTION
PUB RAM_Mode
dira[pin_AUDRST]~~ 'RST now an output
outa[pin_AUDRST] := 0 'RST pulled low
repeat 10
ClockPulse
dira[pin_AUDRST]~ 'restore RST to input, pulled high by external resistor
repeat 10 'these clocks probably not needed,
ClockPulse 'but I guess they can't hurt
PUB ReadByte | temp1, temp2
repeat 5 'probably only one clock pulse is needed here?
ClockPulse
outa[pin_AUDSYNC] := 0 'SYNC pulled low
' send 0000
outa[pin_AUDATA3] := 0
outa[pin_AUDATA2] := 0
outa[pin_AUDATA1] := 0
outa[pin_AUDATA0] := 0
ClockPulse
' send command to read byte (1000) ... read longword is 1010
outa[pin_AUDATA3] := 1
outa[pin_AUDATA2] := 0
outa[pin_AUDATA1] := 0
outa[pin_AUDATA0] := 0
ClockPulse
temp1 := Addr 'temp1 = next address to read
repeat 8 'send nibbles 8 times (total 32 bits)
outa[pin_AUDATA3..pin_AUDATA0] := temp1 'send 4 LSBs of address to AUDATA pins
ClockPulse 'clock them out
temp1 := temp1 >> 4 'rotate address right by 4 bits
AUDATA(input) 'prepare AUDATA lines as inputs
debug.str(String(13,10)) 'write address to hyperterminal
debug.hex(Addr,8)
debug.str(String(","))
'read in data until AUD is ready (0001)
i := 0
repeat
i++
temp := 0
ClockPulse
temp := ina[pin_AUDATA3..pin_AUDATA0] 'read in the data
until temp == %00000001 or i == 10
outa[pin_AUDSYNC] := 1 'SYNC pulled high
if i <> 10 'i.e. 7052 is ready and no errors
temp1 := 0
temp2 := 0
repeat 2 'read 4-bit nibbles from AUDATA lines
temp1 := temp1 << 4 'shift temp1 4 bits to the left
ClockPulse 'clock in the next set of AUDATA bits
temp2 := 0 'clear temp2
temp2 := ina[pin_AUDATA3..pin_AUDATA0] 'temp2 = received data from the ECU
temp1 := temp1 | temp2 'temp2 added on to the shifted temp1 value
ReadBits := temp1 'store result in ReadBits
debug.hex(ReadBits,8)
debug.str(String(","))
AUDATA(output) 'restore AUDATA pins to outputs
PUB ClockPulse
'send clock low then high
waitcnt(clkfreq/(clkrate/2) + cnt)
outa[pin_AUDCK] := 0
waitcnt(clkfreq/clkrate + cnt)
outa[pin_AUDCK] := 1
waitcnt(clkfreq/(clkrate/2) + cnt)
PUB AUDATA(direction)
if direction == input
dira[pin_AUDATA0]~
dira[pin_AUDATA1]~
dira[pin_AUDATA2]~
dira[pin_AUDATA3]~
if direction == output
dira[pin_AUDATA0]~~
dira[pin_AUDATA1]~~
dira[pin_AUDATA2]~~
dira[pin_AUDATA3]~~[/color]